Import a design.
Give it a spec.
Get PVT‑certified.

Schemline is an AI-driven optimization engine for analog ICs — built to fit your existing flow, not replace it. Bring your schematic (Xschem import included), declare the spec, and Schemline sizes and certifies the design across all 6 process/voltage/temperature corners.

OTA
ac_tb
Schemline schematic editor showing OTA circuit
Schemline AIOptimizing...
Gain62.3 dB
Bandwidth5.2 MHz
Phase Margin64°
Noise Figure4.1 dB
SKY130 PDK NGSPICE PYTHON QT 6 CROSS-PLATFORM
AI layer
85 orchestrated tools: topology detection, automatic testbench synthesis, coordinate-descent optimization, gm/Id sizing, operating-region verification, waveform analysis, PCell/layout editing, spec-driven convergence
Simulation
7 analysis types: DC, AC, Transient, Noise, Monte Carlo, Corner, Parametric Sweep. Persistent ngspice backend with batch execution for multi-run sweeps
Library
38 Sky130A primitives: full SPICE model set, schematic symbols, hierarchical subcircuits with Manhattan wire routing
PVT coverage
7 of 10 amplifier topologies certified: 0 spec failures across all 6 process corners (TT/SS/FF/SF/FS × hot/cold) — a native corner workflow LTspice and Xschem don’t offer
How it works

Three steps to a certified circuit

Schemline is an optimization engine, not a CAD replacement — it plugs into the flow you already have.

1. Import your design

Start from a schematic you already have — hand-built, imported from Xschem, or drawn from scratch in Schemline’s own editor. No migration, no rewrite: Schemline reads the circuit as it is.

Xschem importSky130 PDK
OTA
Schemline schematic editor with an imported OTA design

2. Give it a spec

Tell Schemline AI the target in plain language — gain, bandwidth, phase margin, quiescent current. It detects the topology and plans the optimization; you never touch a solver setting.

85 toolsTopology detection

3. Get a PVT-certified design

Schemline resizes the circuit and re-checks every spec across all 6 process, voltage, and temperature corners — TT, FF, SS, SF, FS, hot and cold — until every cell in the matrix reads pass.

6-corner PVT7 of 10 topologies certified
Live demo

See Schemline in action

A walkthrough of the editor, ngspice simulation, and AI assistant on a real Sky130 design — end to end.

The Problem

The €100k gap in chip design

99% of hardware teams can’t afford professional analog design tools. The market has two extremes and nothing in between.

Free Tier
€0
Manual everything. No AI, no optimization, no modern UI. Hours of hand-tuning for every design iteration.
KiCad · ngspice CLI · Xschem
Schemline fills this gap
€0 – 5k/yr
AI-native design. Modern editor, automated optimization, professional simulation: from free academic licenses to affordable startup plans.
Schematic + Sim + AI + PDK
Enterprise
€100k+/yr
Powerful but prohibitively expensive. 1990s interface. Requires dedicated IT infrastructure and seat licenses.
Cadence Virtuoso · Synopsys
Features

Everything you need for analog exploration

A complete design environment: schematic capture, ngspice simulation, and AI-driven optimization.

Schematic Editor

Virtuoso-style wire routing with Manhattan geometry, hierarchical subcircuits, and drag-and-drop from the Sky130 component library. Import existing Xschem schematics directly — hierarchy, orientation, and bus expansion preserved. Familiar to experienced designers, approachable for newcomers.

Sky130 PDK38 cellsHierarchicalXschem import
OTA
ac_tb
Schemline schematic editor with AI circuit topology detection

Simulation Engine

Persistent ngspice backend with batch execution for multi-run sweeps. DC, AC, Transient, Noise, Monte Carlo, corner, and parametric sweep analysis, all from one unified interface with binary rawfile parsing.

7 analysis typesMonte CarloProcess cornersPVT certified
ac_tb
Schemline waveform viewer showing AC gain and phase analysis

AI Assistant

85 specialized tools orchestrated by an LLM. Topology detection, automatic testbench synthesis, coordinate-descent optimization. Type your specs and let Schemline AI do the job for you autonomously.

85 toolsAuto-optimizationTopology detection

gm/Id Design Tool

Native gm/Id methodology, not a plugin. Lookup tables, 4-panel visualization, and a joint multi-device solver that sizes matched devices — current mirrors, cascodes, differential pairs — together instead of one at a time. Every proposed change is checked against a physics-based gate before it’s applied to the schematic.

Native methodologyMulti-device solverRegression-safe sizing
gm/Id
Schemline gm/Id design methodology with 4-panel visualization and sizing calculator
Comparison

How Schemline compares

The features that matter for modern analog design.

FeatureSchemlineCadenceLTspiceXschem
AI-Ready Architecture✓ Native
Circuit Structure Recognition✓ Built-in
gm/Id Methodology✓ Native⚠ Plugin
Xschem Schematic Import✓ Native✓ (native format)
Modern UI✓ Qt6✗ Legacy⚠ Basic
Cross-Platform✓ All⚠ Linux⚠ Windows
Free for Academia✓ Free✓ Free✓ Free
Monte Carlo / Corners✓ 6-corner
PriceFree – €5k€50k–200kFreeFree
Business Model

A market with no middle ground

98% of the analog EDA market is split between tools that are free but manual, and tools that cost €100k+/yr. Schemline captures the underserved segment in between with a three-tier SaaS model.

Academia
Free
University labs and open-source projects. Serves as the primary pipeline for future startup and enterprise customers.
  • Full schematic editor
  • All simulation types
  • Sky130A PDK
  • Community support
Enterprise
€10k+ /year
Expansion revenue. Mid-size companies moving off legacy tools or requiring commercial PDK support alongside Schemline.
  • Everything in Startups
  • TSMC/GF PDK support
  • Dedicated account manager
  • On-premise deployment

Final pricing set at launch. Global EDA software market: $12B+. Target segment: analog design tools, est. €500M.

Talk to the team

Schemline is in private development ahead of a public launch. Reach out to discuss the technology, the market, or the roadmap.

Request a Meeting →