The first
AI-native analog
IC design platform

A full-stack AI-native analog IC design platform: schematic editor, ngspice simulation, and LLM-orchestrated optimization. Targeting the €500M segment between free open-source tools and €100k/yr legacy EDA.

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OTA
ac_tb
Schemline schematic editor showing OTA circuit
Schemline AI Optimizing...
Gain62.3 dB
Bandwidth5.2 MHz
Phase Margin64°
Noise Figure4.1 dB
SKY130 PDK NGSPICE PYTHON QT 6 CROSS-PLATFORM
AI layer
28 orchestrated tools: topology detection, automatic testbench synthesis, coordinate-descent optimization, gm/Id sizing, operating-region verification, waveform analysis
Simulation
6 analysis types: DC, AC, Transient, Noise, Monte Carlo, Corner. Persistent ngspice backend with batch execution for multi-run sweeps
Library
38 Sky130A primitives: full SPICE model set, schematic symbols, hierarchical subcircuits with Manhattan wire routing
Validation
1,050 automated tests across wire routing, simulation accuracy, AI tool correctness, and UI components
Live demo

See Schemline in action

A walkthrough of the editor, ngspice simulation, and AI assistant on a real Sky130 design — end to end.

The Problem

The €100k gap in chip design

99% of hardware teams can’t afford professional analog design tools. The market has two extremes and nothing in between.

Free Tier
€0
Manual everything. No AI, no optimization, no modern UI. Hours of hand-tuning for every design iteration.
KiCad · ngspice CLI · Xschem
Schemline fills this gap
€0 – 5k/yr
AI-native design. Modern editor, automated optimization, professional simulation: from free academic licenses to affordable startup plans.
Schematic + Sim + AI + PDK
Enterprise
€100k+/yr
Powerful but prohibitively expensive. 1990s interface. Requires dedicated IT infrastructure and seat licenses.
Cadence Virtuoso · Synopsys
Features

Everything you need for analog exploration

A complete design environment: schematic capture, ngspice simulation, and AI-driven optimization.

Schematic Editor

Virtuoso-style wire routing with Manhattan geometry, hierarchical subcircuits, and drag-and-drop from the Sky130 component library. Familiar to experienced designers, approachable for newcomers.

Sky130 PDK 38 cells Hierarchical
OTA
ac_tb
Schemline schematic editor with AI circuit topology detection

Simulation Engine

Persistent ngspice backend with batch execution for multi-run sweeps. DC, AC, Transient, Noise, Monte Carlo, and corner analysis, all from one unified interface with binary rawfile parsing.

6 analysis types Monte Carlo Process corners
ac_tb
Schemline waveform viewer showing AC gain and phase analysis

AI Assistant

28 specialized tools orchestrated by an LLM. Topology detection, automatic testbench synthesis, coordinate-descent optimization. Type your specs and Schemline AI converges in seconds.

28 tools Auto-optimization Topology detection
Schemline AI assistant optimizing an OTA circuit

gm/Id Design Tool

Native gm/Id methodology, not a plugin. Lookup tables, 4-panel visualization, and a sizing calculator that integrates directly with the optimization engine.

Native methodology Sizing calculator
gm/Id
Schemline gm/Id design methodology with 4-panel visualization and sizing calculator
Comparison

How Schemline compares

The features that matter for modern analog design.

FeatureSchemlineCadenceLTspiceXschem
AI-Ready Architecture✓ Native✗✗✗
Circuit Structure Recognition✓ Built-in✗✗✗
gm/Id Methodology✓ Native⚠ Plugin✗✗
Modern UI✓ Qt6✗ Legacy⚠ Basic✗
Cross-Platform✓ All⚠ Linux⚠ Windows✓
Free for Academia✓ Free✗✓ Free✓ Free
Monte Carlo / Corners✓✓✗✗
PriceFree – €5k€50k–200kFreeFree
Business Model

A market with no middle ground

98% of the analog EDA market is split between tools that are free but manual, and tools that cost €100k+/yr. Schemline captures the underserved segment in between with a three-tier SaaS model.

Academia
Free
University labs and open-source projects. Serves as the primary pipeline for future startup and enterprise customers.
  • Full schematic editor
  • All simulation types
  • Sky130A PDK
  • Community support
Startups & SMEs
€3–5k /year
Primary revenue segment. Fabless hardware startups unable to justify Cadence licensing, needing AI-assisted design and professional simulation.
  • Everything in Academia
  • AI optimization (unlimited)
  • Priority support
  • Cloud simulation
Enterprise
€10k+ /year
Expansion revenue. Mid-size companies moving off legacy tools or requiring commercial PDK support alongside Schemline.
  • Everything in Startups
  • TSMC/GF PDK support
  • Dedicated account manager
  • On-premise deployment

Pricing finalised at Q3 2026 launch. Global EDA software market: $12B+. Target segment: analog design tools, est. €500M.

Talk to the team

Schemline is in private development ahead of a Q3 2026 launch. Reach out to discuss the technology, the market, or the roadmap.

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